clocked RS-filpflop by 3 input gates
-- Q(n+1) = CK * S + not(P(n))
-- P(n+1) = CK * R + not(Q(n))
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity top_level is
port (
S, R, CK : in std_logic;
Q, nQ : buffer std_logic
);
end entity;
architecture IMP of top_level is
component three_input_gate
port (
CK, S, P : in std_logic;
Q : out std_logic
);
end component;
begin
U1 : three_input_gate
port map(
CK => CK,
S => S,
P => nQ,
Q => Q
);
U2 : three_input_gate
port map(
CK => CK,
S => R,
P => Q,
Q => nQ
);
end IMP;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity three_input_gate is
port (
CK, S, P : in std_logic;
Q : out std_logic
);
end entity;
architecture IMP of three_input_gate is
begin
Q <= (not P) or (CK and S);
end IMP;