ADS 805 驱动代码
/**
* @brief ads805 interface
* @param [out] ad_dclk AD时钟
* @note 6个时钟后才是本次触发的对应值
*/
module ads805_intf #(
parameter DATA_WIDTH = 12
) (
input clk,
input rst_n,
input en_pulse,
input start,
input [DATA_WIDTH-1:0] ad_dout,
output reg ad_dclk,
output reg [DATA_WIDTH-1:0] ad_res,
output reg drdy
);
localparam HIG = 1'b1;
localparam LOW = 1'b0;
localparam NOT_READY = 1'b0;
localparam READY = 1'b1;
localparam STATE_WIDTH = 3;
localparam S_SCAN_WAIT_AD_UP = 3'b001;
localparam S_SCAN_WAIT_AD_UPDOWN_DCLK = 3'b010;
localparam S_SCAN_WAIT_AD_UPUP_DCLK = 3'b100;
reg[STATE_WIDTH-1:0] state;
reg[STATE_WIDTH-1:0] next_state;
initial
begin
ad_dclk <= 0;
ad_res <= 0;
state <= 0;
drdy <= 0;
end
always @ (negedge rst_n or posedge clk)
begin
if (!rst_n)
state <= S_SCAN_WAIT_AD_UP;
else if (en_pulse)
state <= next_state;
end
always @ (*)
begin
next_state = S_SCAN_WAIT_AD_UP;
case (state)
S_SCAN_WAIT_AD_UP:
begin
if(start)
next_state = S_SCAN_WAIT_AD_UPUP_DCLK;
else
next_state = S_SCAN_WAIT_AD_UP;
end
S_SCAN_WAIT_AD_UPUP_DCLK:
begin
next_state = S_SCAN_WAIT_AD_UPDOWN_DCLK;
end
S_SCAN_WAIT_AD_UPDOWN_DCLK:
begin
if(start)
next_state = S_SCAN_WAIT_AD_UPUP_DCLK;
else
next_state = S_SCAN_WAIT_AD_UP;
end
default:
begin
next_state = S_SCAN_WAIT_AD_UP;
end
endcase
end
always @ (negedge rst_n or posedge clk)
begin
if (!rst_n)
begin
ad_dclk <= LOW;
ad_res <= {DATA_WIDTH{1'b0}};
drdy <= NOT_READY;
end
else if (en_pulse)
begin
case(next_state)
S_SCAN_WAIT_AD_UP:
begin
ad_dclk <= LOW;
drdy <= NOT_READY;
end
S_SCAN_WAIT_AD_UPUP_DCLK:
begin
ad_dclk <= HIG;
drdy <= NOT_READY;
end
S_SCAN_WAIT_AD_UPDOWN_DCLK:
begin
ad_dclk <= LOW;
ad_res <= ad_dout;
drdy <= READY;
end
default:
begin
ad_dclk <= LOW;
ad_res <= {DATA_WIDTH{1'b0}};
drdy <= NOT_READY;
end
endcase
end
end
endmodule